The present invention generally relates to an electrode assembly useful in confined plasma assisted chemical etching and, in particular, relates to one such electrode assembly having means for providing a D.C. bias voltage to the electrode.
As used herein the phrase "confined plasma" is taken to means a plasma discharge that is laterally bounded such that the spatial footprint of the plasma can be controlled.
A general theory of the physical factors involved in the plasma assisted chemical etching process is provided in the article entitled A Theory of Plasma-Assisted Chemical Vapor Transport Processes; by C. B. Zarowin in the Journal of Applied Physics, 57(3), Feb. 1, 1985. Therein a set of mathematical equations are developed that describe the factors involved in the flow of the plasma. Among other factors discussed therein is the effect of the external application of, or self-induced, dc bias are discussed as having effects similar to that of temperature differences in that both superpose algebraically in the transport rate.
Recently, the use of plasma assisted chemical etching has been applied to both the thinning and flattening of semiconductor wafers. In such applications a confined plasma is established between a relatively small area electrode, or puck, and a larger electrode. The semiconductor wafer is disposed between the puck and the larger electrode and is the thinned or flattened by creating relative motion between the semiconductor wafer and the puck in accordance with a predetermined dwell time map. In order to achieve a highly accurate process, the plasma discharge is confined so that the operating plasma etching footprint is smaller than the smallest surface variation to be etched.
As well known in the semiconductor wafer processing art, it is extremely important at each step of the semiconductor wafer processing to avoid the contamination of the semiconductor wafer surface. A typical semiconductor industry surface cleanliness specification is less than 2 particles greater than 0.1 micrometer in diameter over the entire surface of a wafer. Hence, considerable time and expense are used to ensure that the surface of the semiconductor wafer is as free of particulates as possible.
Presently, electrode assemblies include an electrode formed from a porous electrically conductive material and disposed at one end of an electrode holder. An electrically insulating chimney is disposed such that the electrode extends partially through a clearance opening in the chimney. The porous conductive material allows the flow of an etchant gas through the electrode to sustain the plasma. The surrounding chimney helps to ensure the desired lateral confinement of the plasma discharge. In operation, it has been found that both the puck electrode and the chimney are subject to a relatively high rate of erosion. The erosion is primarily caused by high energy ions impinging upon the electrode and chimney. Further, because the opening in the chimney is a clearance opening, there is a gap between the electrode and the walls of the chimney opening. This gap can result in the sputtering of the electrode thereby creating a source of contamination.
Further, the erosion of the puck electrode and the surrounding chimney not only greatly reduces the operating life of those components but also serves as a source of contamination of the semiconductor wafer surface.
Hence, it is highly desirable to provide an electrode assembly that has a comparatively longer life and which reduces the in-process contamination of the semiconductor wafer surface.